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Diagnosing Yield Detractors on a Large Scale Integrated Circuit Manufacturing Line

IP.com Disclosure Number: IPCOM000082279D
Original Publication Date: 1974-Nov-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Haddad, NF: AUTHOR [+3]

Abstract

Historically, test sites have been used to evaluate yield detractors on an integrated circuit manufacturing line. The test site is not sensitive to defect types or density variations, other than those for which it was designed. It is proposed that a complex random-access memory array be used as a vehicle to measure defect types and densities on analog, logic and array manufacturing lines.

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Diagnosing Yield Detractors on a Large Scale Integrated Circuit Manufacturing Line

Historically, test sites have been used to evaluate yield detractors on an integrated circuit manufacturing line. The test site is not sensitive to defect types or density variations, other than those for which it was designed. It is proposed that a complex random-access memory array be used as a vehicle to measure defect types and densities on analog, logic and array manufacturing lines.

The array chips are processed at the same time as the normal product mix. The array, which is completely addressable to locate all defect types, is tested and fail locations noted (on failing chips). These array fails are then analyzed physically and electrically to determine the defect type or mechanism.

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