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Lateral PNP Design for Memory Cell

IP.com Disclosure Number: IPCOM000082285D
Original Publication Date: 1974-Nov-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Dorler, JA: AUTHOR [+3]

Abstract

The memory cell shown in Fig. 1 utilizes a complementary transistor switch (CTS), in which lateral PNP and NPN devices simultaneously drive and act as a load for each other.

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Lateral PNP Design for Memory Cell

The memory cell shown in Fig. 1 utilizes a complementary transistor switch (CTS), in which lateral PNP and NPN devices simultaneously drive and act as a load for each other.

For purpose of illustrating the utility of the CTS device design, assume side B in Fig. 1 is conducting and side A is being held off. To change state of the cell, the write input WA on the off side A is excited by a negative current pulse, IA. As a first order approximation, the minimum requirement on IA necessary to cause switching of side A is BpIk, where Bp is the effective current gain of the lateral PNP device and Ik is the cell bias current provided by the constant-current source. In practice, current overdrive is used such that IA >>BpIk for high-speed switching; this implies that, for the lateral PNP to be practical, a low Bp device is a must.

To be more specific, the efficient cell switching requires certain PNP device characteristics, namely, a low Bp which peaks at the relatively low-standby current for cell stability, and falls off sharply above this current so as to minimize the IA requirement.

By constructing a lateral PNP, as shown in Fig. 2A, certain measures can be taken to ensure low Bp. Fig. 2B shows a more appropriate schematic of a lateral PNP, employing some of these measures. The shunting diode D, which exists between the emitter and base is a function of the lateral area of the PNP emitter, while the PNP normal emitter area is a funct...