Browse Prior Art Database

Logic and Extend Function

IP.com Disclosure Number: IPCOM000082286D
Original Publication Date: 1974-Nov-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Gani, VL: AUTHOR [+3]

Abstract

Provision is made for increasing the number of inputs to an AND circuit, where the masterslice logic circuit cell layout provides for a maximum of four inputs via a multiple-emitter transistor per logic cell.

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Logic and Extend Function

Provision is made for increasing the number of inputs to an AND circuit, where the masterslice logic circuit cell layout provides for a maximum of four inputs via a multiple-emitter transistor per logic cell.

Where applications dictate an AND function having more than four inputs, a viable method of providing the additional inputs, on or off-chip, is to connect a portion of another cell as depicted in the drawing.

The cells chosen to perform the AND extend function should be as closely spaced as possible to minimize wiring capacitances.

The collectors of transistors T1 and T3 are connected in common to the base of transistor T2. Referring to the drawing, it will be noted that only a selected portion of the circuitry of cell 2 is connected to cell 1.

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