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Chip Communicating Circuit

IP.com Disclosure Number: IPCOM000082287D
Original Publication Date: 1974-Nov-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 91K

Publishing Venue

IBM

Related People

Klara, WS: AUTHOR [+2]

Abstract

The power send configuration illustrated in Fig. 1 provides increased noise tolerance, circuit performance and the capability of driving long heavily loaded nets. Its implementation on a master-slice is illustrated in Figs. 2A and 2B.

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Chip Communicating Circuit

The power send configuration illustrated in Fig. 1 provides increased noise tolerance, circuit performance and the capability of driving long heavily loaded nets. Its implementation on a master-slice is illustrated in Figs. 2A and 2B.

In Fig. 2A, input via pairs P0-P4 P1-P5, etc. which parallel the emitter inputs are made common by vias from 1st to 2nd level metallization. Outputs D1-D2, common the collector output of the power internal and also connect to the base of the power send (Fig.2B) by chip metallization, or to other internal circuits for increased performance and/or fan-out capability.

The bases, emitters and collectors of the power send are made common by a combination of vias and metallization patterns, as required for circuit implementation.

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