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Power Supplies Current Drain Test Method

IP.com Disclosure Number: IPCOM000082291D
Original Publication Date: 1974-Nov-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Kaufman, CL: AUTHOR [+3]

Abstract

Technology chips are tested by applying a series of parametric and functional tests. The first of such tests is the Power Supplies Current Drain Test. Its purpose: to ensure that the power supplies currents remain within certain limiting values, beyond which the probes of the tester are permanently damaged. These currents usually exceed those limits as a result of some failure inside of the chip, which provides a low-impedance path to an input or output. This causes the burning of a probe.

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Power Supplies Current Drain Test Method

Technology chips are tested by applying a series of parametric and functional tests. The first of such tests is the Power Supplies Current Drain Test. Its purpose: to ensure that the power supplies currents remain within certain limiting values, beyond which the probes of the tester are permanently damaged. These currents usually exceed those limits as a result of some failure inside of the chip, which provides a low-impedance path to an input or output. This causes the burning of a probe.

Since no theoretical calculations enter in the sizing up of those currents, the limiting values are arrived at by some educated guess on the magnitude of the "highest safe value" that a power supply current may take before harming the probes.

A more accurate test is introduced to eliminate the limitations of the old test. It also extends its capabilities to immediate screening out of defective product. The new test consists of:

1. Determining by simulation how many circuits in the chip are in the "on" and the "off" state, after applying one or several known test patterns to the chip inputs.

2. Calculating with accuracy all the power supply currents as a function of the number of circuits that are on or off.

3. Applying those same test patterns to the chip at testing time under the umbrella of the "highest safe current values", as it was done in the old test.

4. Comparing the measured (power supplies) currents with the theoretical values...