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Two Phase Dynamic Frequency Divider

IP.com Disclosure Number: IPCOM000082300D
Original Publication Date: 1974-Nov-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Glaise, R: AUTHOR

Abstract

This description is directed to a method for designing frequency dividers using two-phase dynamic shift register cells. Such a shift register cell comprises two inverters and two transmission gates TG controlled by two nonoverlapping clock phases phi 1 and phi 2.

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Two Phase Dynamic Frequency Divider

This description is directed to a method for designing frequency dividers using two-phase dynamic shift register cells. Such a shift register cell comprises two inverters and two transmission gates TG controlled by two nonoverlapping clock phases phi 1 and phi 2.

Fig. 1 shows a conventional frequency divider using two series connected cells and providing division of the clock frequency by four. This divider by four may have four different starting states, but provides a division by four in all cases.

However, dividers by more than four designed in this way present an operating instability.

To avoid this instability, dividers are implemented with feedback paths as schematically shown in Fig. 2. The optimization studies result in the following conclusions where DIV is the division ratio:

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The proposed method permits the determination of the number of feedback paths which are necessary to have a good division in any starting case. The study result is that the number P of feedback paths must be at least equal to half the number Nm of possible feedbacks with N transmission gates TG. As Nm = N/2, we must have:. P >/- N/4 (3).

By combining (1) and (3), it is possible to obtain the optimum number of gates TG, N, and the number of feedback paths P, for a given division ratio DIV. Thus we have:

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