Browse Prior Art Database

Address Circuit Checking

IP.com Disclosure Number: IPCOM000082301D
Original Publication Date: 1974-Nov-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Deuerlein, A: AUTHOR [+4]

Abstract

This data bus has the width of a halfword, i.e., two bytes, which is stored in a memory array marked right and left, respectively.

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Address Circuit Checking

This data bus has the width of a halfword, i.e., two bytes, which is stored in a memory array marked right and left, respectively.

For checking the address circuits, parity bits P of the right and left byte are interchanged before storing and again after having been read. If during addressing one or both array addresses are faultily generated, this is detected by the parity check circuits after reading. These check circuits generate a parity bit for the read data byte, comparing it with the parity bit taken from the other byte read.

A single-addressing fault stands a 75$ chance of being detected, because of the four possibilities data byte odd or even, parity bit 1 or 0) for a byte stored in an array, only one fits one of the four combinations of the byte stored in the other array.

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