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Self Adjusting Signal Delay Generation on LSI Circuit Chips

IP.com Disclosure Number: IPCOM000082304D
Original Publication Date: 1974-Nov-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Schmidt, W: AUTHOR

Abstract

Clock generator networks frequently have to supply signals that have a predetermined delay over a reference signal So. To generate such a delayed signal Sd by large-scale integration (LSI) circuits, the signal delay occurring during the passage of a chain of logic circuits is employed.

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Self Adjusting Signal Delay Generation on LSI Circuit Chips

Clock generator networks frequently have to supply signals that have a predetermined delay over a reference signal So. To generate such a delayed signal Sd by large-scale integration (LSI) circuits, the signal delay occurring during the passage of a chain of logic circuits is employed.

The characteristic signal delay of the logic circuits of a chip is measured by the output pulses of a ring oscillator produced on the chip being applied for a predetermined period of time, via an AND gate, to a binary counter which is also produced on the chip. The count is used to control a delay chain made up of several parts and produced on the chip. In this delay chain each succeeding part is twice as long as the preceding one to which it is linked via a NAND gate.

Activation of a number of delay units DU of the chain, which number is proportional to the count, ensures that the signal delay is invariably the same, even in cases where different chips have different signal delays, since the count is a function of the chip specific signal delay.

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