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Inverse Exclusive or Circuit for Dynamic Logic

IP.com Disclosure Number: IPCOM000082311D
Original Publication Date: 1974-Nov-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Lau, LR: AUTHOR [+3]

Abstract

This circuit provides the inverse exclusive OR function previously disclosed by T. S. Jen in the IBM Technical Disclosure Bulletin, Vol. 8, No. 8, January 1966 at pages 1156-1157.

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Inverse Exclusive or Circuit for Dynamic Logic

This circuit provides the inverse exclusive OR function previously disclosed by T. S. Jen in the IBM Technical Disclosure Bulletin, Vol. 8, No. 8, January 1966 at pages 1156-1157.

Circuit 30 has a switched field-effect transistor (FET) load device 24 to precharge output node 22 to an up binary level during phase one time. Switching FET devices 12 and 14 are cross coupled, source-to-gate, as shown so that a path is provided from node 22 via node 26 or node 28 to ground, only if an exclusive OR function is satisfied at the inputs 26 and 28. The exclusive OR circuit 30 can be driven by any dynamic logic gate, exemplified by dynamic logic inverters 18 and 20.

During phase one time, precharge transistors 2, 4, and 24 precharge nodes 26, 28, and 22 to approximately +V. During phase 2, transistors 6, 10 and transistors 8, 16 provide discharge paths through the inputs 26 and 28, respectively, if a positive level signal A or B is present at the gates of transistors 10 and 16. If both nodes 26 and 28 are discharged to a ground level, the gates of transistors 14 and 12 will also be deconditioned, and transistors 14 and 12 will not discharge node 22.

If signals A and B are both at a down level, both nodes 26 and 28 will not be discharged but will remain at approximately +V, allowing the gates of transistors 12 and 14 to be activated. However, no discharging current will flow from node 22, because the source and drain of transist...