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Silicon Controlled Rectifier Gate Drive Circuit

IP.com Disclosure Number: IPCOM000082315D
Original Publication Date: 1974-Nov-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Felton, BC: AUTHOR [+3]

Abstract

In some silicon-controlled rectifier (SCR) gate driver circuits there exists a requirement for an isolated, fast rise and fall, long duration drive signal. This circuit utilizes pulse transformers so as to provide the fast rise characteristics. Full-wave operation provides a combined output which can have an unlimited duration. The configuration chosen is push-push, which precludes core walking and attendant problems, thereby allowing fast turnoff.

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Silicon Controlled Rectifier Gate Drive Circuit

In some silicon-controlled rectifier (SCR) gate driver circuits there exists a requirement for an isolated, fast rise and fall, long duration drive signal. This circuit utilizes pulse transformers so as to provide the fast rise characteristics. Full-wave operation provides a combined output which can have an unlimited duration. The configuration chosen is push-push, which precludes core walking and attendant problems, thereby allowing fast turnoff.

The drive circuit utilizes a pair of switching transistors Q1, Q2 which admit +V to primary windings 10, 12 of pulse transformers T1 and T2, respectively, when Q1 and Q2 are driven on. The drive signals applied to terminals 14, 16 are of the form shown schematically at 18, 20, respectively.

When Q1 is on, current flows by the power of +V through primary 10, thereby inducing a potential in secondary 22 of T1 of a polarity to cause current to flow through rectifier diode 24 and the gate input resistor 26 of controlled rectifier 28. If 28 is supplied by a forward potential applied at terminal 30, it will conduct as indicated at 32. The gate circuit of rectifier 28 is provided with the usual off-bias resistor 34. When the forward drive signal 18 falls, Q1 turns off and T1 starts to reset.

To control reset, a third winding 36 is provided on T1, connected between +V return (ground) and through diode 38 to +V. Diode 38 conducts during T1 reset and limits the rise of the Q1 collector voltage. This type of reset clamp is well adapted to burst operation of the pulse transformer. In a typical arrangement the transformer is wound on a three-space bobbin with...