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Testable Off Chip Drivers

IP.com Disclosure Number: IPCOM000082343D
Original Publication Date: 1974-Nov-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Bodner, RE: AUTHOR [+2]

Abstract

The current carrying capacity of off-chip drivers is limited. Although, the drivers can be connected in parallel to increase the drive current, if this is done off chip an output pin is required for each driver. Connecting the drivers in parallel on chip decreases the number of output pins used, but makes the testing of the drivers difficult. The solution to the testing problem is to separately control the paths through the off-chip drivers.

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Testable Off Chip Drivers

The current carrying capacity of off-chip drivers is limited. Although, the drivers can be connected in parallel to increase the drive current, if this is done off chip an output pin is required for each driver. Connecting the drivers in parallel on chip decreases the number of output pins used, but makes the testing of the drivers difficult. The solution to the testing problem is to separately control the paths through the off-chip drivers.

In the drawing, the outputs of off-chip drivers 15, 25 and 35 are commonly connected on chip by dot 40 which leads to output pin 45. Inputs A and B and, the absence of test signals Test 1, Test 2 and Test 3 to AND circuits 10, 20 and 30, respectively, normally activate drivers 15, 25 and 35 simultaneously.

When in a test mode, however, a test signal blocks the associated AND circuit. Hence, to test driver 15 test signals Test 2 and Test 3 are applied to AND circuits 20 and 30, respectively. A signal will then appear at output 45 only if AND circuit 10 and off-chip driver 15 are operating properly. Drivers 25 and 35 are tested in a similar manner, i.e., to test driver 25 test signals Test 1 and Test 3 are activated and to test driver 35 test signals Test 1 and Test 2 are activated.

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