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Addressing of Different Size Storage Modules

IP.com Disclosure Number: IPCOM000082344D
Original Publication Date: 1974-Nov-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Crooks, TL: AUTHOR [+2]

Abstract

An addressing arrangement is provided for data storages having modules of different densities. The two different storages can be in the same machine or one can be a replacement of the other.

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Addressing of Different Size Storage Modules

An addressing arrangement is provided for data storages having modules of different densities. The two different storages can be in the same machine or one can be a replacement of the other.

Data storage 10, Fig. 1, consists of eight modules each having 512 bits; while data storage 20 has four modules each having 1024 bits. A common address register (SAR) 25 is supplied with addresses for addressing either data storage 10 or 20.

The significance of certain address bits in SAR 25 changes depending upon the density of the storage being addressed. When storage 10 is addressed, bits 0-3 are decoded by card select logic 26 under control of storage type controls 27 for selecting 1 of N cards or modules, where in this instance N can equal 1 to 16. Bit 4 is decoded by Y Decode logic 28 into two Y select lines. Four X selection lines result from the decode of bits 5 and 6 by X Decode logic 29. Bits 7-15 inclusive are passed by gate 31 under control of 27 to select 1 of 512 bits. The decode of the bits 7-15 takes place within the card or module. Storage clocks 35 provide the signals, having a time relationship as shown by the dotted lines in Fig. 2, for operating storage 10.

When storage 20 is addressed as determined by controls 27, bits 0-2 of SAR 25 are decoded by card select logic 26 to form M card or module select lines, where M can equal 1 to 8. Bit 4 is decoded by logic 28 into two Y selection lines as above. Four X select...