Browse Prior Art Database

Testing of Off Card Drivers

IP.com Disclosure Number: IPCOM000082350D
Original Publication Date: 1974-Nov-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Woessner, RJ: AUTHOR

Abstract

A circuit arrangement is provided for testing off-chip drivers under program control. A list of possible card failures is first developed by test patterns. Program testing then determines the failing card.

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Testing of Off Card Drivers

A circuit arrangement is provided for testing off-chip drivers under program control. A list of possible card failures is first developed by test patterns. Program testing then determines the failing card.

Off-chip drivers 20-24, as shown in the drawing, are fed by output latches 15- 19, respectively, of latch pairs of the type described in Patent 3,806,891 which form a register 14.

In order to test for drivers stuck in the zero state, the test program loads register 14 with binary 1's. Test latch 10 is then set under program control to condition AND circuit 12. The first position of register 14 is normally set under control of AND circuit 11.

For testing purposes, AND circuit 12 and OR circuit 13 together with latch 10 are added to the circuit. AND circuit 12 receives an input from AND circuits 25 and 26, which have their outputs dotted together and are fed by drivers 20-24. A single AND circuit could replace AND circuits 25 and 26 if the circuit technology used permitted five inputs. Register 14 is then loaded with 0's. If drivers 20-24 are operating properly, the first position of register 14 should remain set under control of AND circuit 12 and all other positions should become reset. Register 14 is then read out by the program by applying a Read Register 1 signal to AND circuits 27 and a value of 10000 should be returned. The program then tests the returned value for error conditions.

Drivers 20-24 are tested for a stuck 1 by firs...