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Estimating Expected Connection Length for LSI Circuit Layouts

IP.com Disclosure Number: IPCOM000082374D
Original Publication Date: 1974-Nov-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 24K

Publishing Venue

IBM

Related People

Donath, WE: AUTHOR

Abstract

This method is concerned with estimating connection lengths for large-scale integration (LSI) chips, in order to estimate wiring space requirements. For this purpose, an average connection length to circuit count relationship for square arrays is used, which was derived earlier as taught in "Relationship Between Logic Size and Wiring Length", W.E. Donath, IBM Research Report RC 1455, (in Appendix 1, a short derivation of the relationship [by interconnection length, means the center-to-center distance in terms of circuit spacing] is given). This relationship is based on Rant's Rule, where Rent's Rule is given as a relationship between expected terminal count T to block count C. (1) T = AC/p/, where A is the average number of terminals on a block and p, the "Rent exponent", is a variable parameter.

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Estimating Expected Connection Length for LSI Circuit Layouts

This method is concerned with estimating connection lengths for large-scale integration (LSI) chips, in order to estimate wiring space requirements. For this purpose, an average connection length to circuit count relationship for square arrays is used, which was derived earlier as taught in "Relationship Between Logic Size and Wiring Length", W.E. Donath, IBM Research Report RC 1455, (in Appendix 1, a short derivation of the relationship [by interconnection length, means the center-to-center distance in terms of circuit spacing] is given). This relationship is based on Rant's Rule, where Rent's Rule is given as a relationship between expected terminal count T to block count C. (1) T = AC/p/, where A is the average number of terminals on a block and p, the "Rent exponent", is a variable parameter.

Both theoretical work as discussed in "Stochastic Model of the Computer Design Process", W. E. Donath, IBM Research Report RC 3136, and experimental work as discussed in "On a pin vs Block Relationship for Partitions of Logic Graphs", B. S. Landman and R. L. Russo, IEEE Trans. on Computers (1971) C-20, pages 1469-1479 (or IBM Research Report RC 3088); "A Relation Between Pin and Circuit Requirements for Digital Logic Packages", B. S. Landman and R. L. Russo, IBM Research Report RC 3102; "Hierarchical Placement of Circuits", W. E. Donath, IBM Design Automation Proceedings, RA- 29, pages 182-192; exist on the Rent relationship.

The formula for the average length R of an interconnection is given as (2A) p not = .5 R = 2 over 9 (1 - 4/p-1/) over (1 - C/p-1) 7 1 - C/p-1/2/ over 1 - 2/2p-1/ - 1 - C/p-3/2 over 1 - 2/2p - 3/ (2B) p = .5...