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MNOS Array Structure with Self Aligned Ion Implantation

IP.com Disclosure Number: IPCOM000082382D
Original Publication Date: 1974-Nov-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Krick, PJ: AUTHOR

Abstract

A problem which has been observed in metal-nitride-oxide semiconductor (MNOS) and metal-alumina-oxide semiconductor (MAOS) variable threshold field-effect transistors (FET's), is the existence of parasitic FET's in parallel with the actual memory elements. This parasitic device action has two sources: (1) the oxide step from the 25 A SiO(2) gate region to the field oxide (5000 angstroms), which runs parallel to the direction of current flow shown by lines A and B in Fig. 1; and (2) the partial switching of the channel region, which is not covered by the gate electrode, due to the fringing of electric field from the gate electrodes.

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MNOS Array Structure with Self Aligned Ion Implantation

A problem which has been observed in metal-nitride-oxide semiconductor (MNOS) and metal-alumina-oxide semiconductor (MAOS) variable threshold field-effect transistors (FET's), is the existence of parasitic FET's in parallel with the actual memory elements. This parasitic device action has two sources: (1) the oxide step from the 25 A SiO(2) gate region to the field oxide (5000 angstroms), which runs parallel to the direction of current flow shown by lines A and B in Fig. 1; and (2) the partial switching of the channel region, which is not covered by the gate electrode, due to the fringing of electric field from the gate electrodes.

The standard device structure when the thin-oxide gate region is completely covered by the gate metal is shown in Fig. 1. This device has parasitic device action, due to the oxide steps A and B which form fixed threshold FET's in parallel with the memory element.

These parasitic devices have thresholds in the 1 to 4 volt range and make it impossible to observe the memory elements high threshold of 8 to 10 volts.

These oxide steps are eliminated by running the thin-oxide region the length of the bit lines as in Fig. 2; but this structure gives rise to the second type of parasitic device action as shown in Fig. 3. In this structure, the fringing fields from the word lines can cause partial switching of the regions designated C. These regions of partial switching can exhibit a lower...