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Dual Level Sense Scheme for Composite Insulator Memory Arrays

IP.com Disclosure Number: IPCOM000082383D
Original Publication Date: 1974-Nov-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 42K

Publishing Venue

IBM

Related People

Krick, PJ: AUTHOR

Abstract

It has been observed that the low-threshold voltage state of metal-nitride-oxide semiconductor (MNOS) memory elements shift slowly, due to the application of the read or interrogate voltage signals. This problem is generally referred to as "read disturb sensitivity". The chip organization and sense scheme described herein eliminates this problem.

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Dual Level Sense Scheme for Composite Insulator Memory Arrays

It has been observed that the low-threshold voltage state of metal-nitride- oxide semiconductor (MNOS) memory elements shift slowly, due to the application of the read or interrogate voltage signals. This problem is generally referred to as "read disturb sensitivity". The chip organization and sense scheme described herein eliminates this problem.

The organization of an MNOS array 1 is shown in Fig. 1, and consists of a conventional 3x3 array of MNOS devices 2 plus an additional monitor device 3 connected to each word line, WL1,WL3, all of which are connected to form a monitor bit line 4 in addition to bit lines, BL1-BL3. Monitor bit line 4 is identical to the other bit lines, except that an associated sense amplifier 5 is referenced to a different voltage and devices 3 in this bit line are always written into the low- threshold state. The array of Fig. 1 uses the conventional MNOS write scheme and n-channel devices are assumed.

The purpose of monitor devices 3 is to determine when the maximum tolerable level of threshold shift due to the application of read pulses has occurred. When this level is reached, sense amplifier 5 on monitor bit line 4 generates a signal which indicates to control circuits on the chip that the word which was just read should be rewritten. Hence, each time a word in the array is read, a monitor device 3 in this word automatically indicates whether the present read cycle should be followed immediately by a write cycle, to restore the low- threshold voltages of the devices associated with the addressed word line. Since monitor device 3 experiences the same number of read cycles as other devices 2 associated with the same word line, there is a close correlation between its threshold shift and the threshold shift in other devices 2 associated with the same word line.

The two basic differences between monitor devices 3 and other devices 2 in array 1 are: (a) monitor devices 3 are always written into the low-threshold state, and (b) during the read cycle, monitor devices 3 are sensed relative to a reference voltage Which determines the magnitude of the tolerable maximum threshold shift. Other devices 2 are sensed relative to ground potential. The exact relat...