Browse Prior Art Database

Contact Barriers to Semiconductor Crystals

IP.com Disclosure Number: IPCOM000082384D
Original Publication Date: 1974-Nov-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 44K

Publishing Venue

IBM

Related People

Brodsky, MH: AUTHOR

Abstract

The device of Fig. 1 has characteristics which are determined by the junction regions between the amorphous semiconductor layer and the crystalline semiconductor layer. These layers are shown as being silicon, although other materials (such as Ge) can be used. The metallurgically vulnerable interface is the one between the amorphous silicon layer and the top metal ohmic contact.

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Contact Barriers to Semiconductor Crystals

The device of Fig. 1 has characteristics which are determined by the junction regions between the amorphous semiconductor layer and the crystalline semiconductor layer. These layers are shown as being silicon, although other materials (such as Ge) can be used. The metallurgically vulnerable interface is the one between the amorphous silicon layer and the top metal ohmic contact.

This device can serve as a useful stable circuit element having properties usually associated with Schottky barrier diodes, for example, rectification switching, carrier injection, photodetection, photovoltaic conversion, etc. The processing steps necessary to make the device are the following. 1) The bottom contact to the single-crystal layer should be a standard ohmic contact, such as sintered aluminum where the semiconductor is silicon. 2) The single-crystal silicon could be a standard p-type wafer with the doping needed for the particular application. Also, it could be a heavily doped p-type wafer with an epi p-type layer on top. The wafer and the epi-layer thicknesses, exact doping and doping profiles, purity, passivating layers, insulating overcoats, etc., are engineering factors to be considered within a broad latitude of parameter values. 3) The amorphous silicon layer should be prepared so that its conductivity contains a significant contribution from hopping at the Fermi level. Typically, evaporation or sputtering at moderate rates (of the order of 10-100 A/second) is adequate. The amorphous silicon thickness must be uniform and thick enough to prevent pinholes or tunneling, but thin enough to cut down on any undesired series resistance due to its bulk resistivity. A thickness of about 3000-6000 angstroms works well. 4) The top metal contact must be chosen so that it makes either good ohmic contact to the amorphous silicon, or that its nonohmicity is such as to be compatible with total device characteristics. That is, if the top electrode is partially rectifying, its forward direction should be the same as the forward biased direction for the total device. In addition, the metal must be chosen so that the metal/amorphous silicon interface is stable under the operating and processing temperatures of the device. For example, aluminum in contact with amorphous silicon cause...