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Reducing the Sheet Resistance of Polysilicon Lines in Integrated Circuits

IP.com Disclosure Number: IPCOM000082393D
Original Publication Date: 1974-Nov-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 51K

Publishing Venue

IBM

Related People

Rideout, VL: AUTHOR

Abstract

In present semiconductor technology, polycrystalline silicon is widely used as an intermediate conductive material for multilayer metallurgy. Unlike other electrical conductors, polysilicon is stable at high temperatures and silicon dioxide (SiO(2)) can be chemically vapor deposited or thermally grown on it. In many integrated circuit applications, long narrow polysilicon lines are used. Examples of such use include charge-coupled device arrays, logic arrays, and one-device memory cell arrays.

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Reducing the Sheet Resistance of Polysilicon Lines in Integrated Circuits

In present semiconductor technology, polycrystalline silicon is widely used as an intermediate conductive material for multilayer metallurgy. Unlike other electrical conductors, polysilicon is stable at high temperatures and silicon dioxide (SiO(2)) can be chemically vapor deposited or thermally grown on it. In many integrated circuit applications, long narrow polysilicon lines are used. Examples of such use include charge-coupled device arrays, logic arrays, and one-device memory cell arrays.

A primary constraint on the circuit speed of these arrays is the relatively high- sheet resistance of polysilicon. The sheet resistance is determined by the concentration of dopant impurities which has a solubility limit. Thus, the solubility limit and the geometrical volume determine the line resistance. The response time of the line to electrical signals is given by the resistance-capacitance product. The capacitance is determined by dielectric constants of the insulators, and by geometrical shapes. It is particularly desirable to decrease the sheet resistance of the polysilicon line to gain increased circuit speed.

In the literature, the use of refractory metals such as Mo and W in place of polysilicon has been discussed. The technological difficulty with refractory metals is that they oxidize during chemical vapor deposition of SiO(2),and these oxides are less stable than SiO(2) thus leading to reliability problems. Of course polysilicon also oxidizes slightly during SiO(2) deposition, but this simply results in the growth of some extra SiO(2).

Metal silicide layers on single-crystal silicon substrates are used in the semiconductor industry to form ohmic contacts and rectifying Schottky barrier contacts. Silicides, which are intermetallic alloys (i.e., metal alloys), are attractive because their formation temperature is compatible with silicon device processing, and because they are electrically stable.

In this description an unusual application of silicide layers is proposed, namely, that the resistance of polysilicon lines can be decreased by forming a high-conductivity silicide layer on the exposed surface of the line. Fig. 1 illustrates the technique for a charge-coupled device array. The metal to be alloyed, that is the polysilicon is deposited over the entire wafer, and the silicide is formed wherever the metal and polysilicon meet. In other areas (e.g., oxide covered areas), the metal remains unreacted and can be removed with an etchant such as aqua regia, whic...