Browse Prior Art Database

Symmetric Partial Addressing

IP.com Disclosure Number: IPCOM000082418D
Original Publication Date: 1974-Dec-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 16K

Publishing Venue

IBM

Related People

Clark, WA: AUTHOR [+2]

Abstract

It is common in memory apparatus to store identification or other address indicia with data. In plural channel recording apparatus, such as multi-track tape, fixed head drum or disk, bubble plates, core memories or plural shift registers, one or more of the plurality of channels can be dedicated to addressing or identification. While in serial devices such as single shift registers, delay lines, movable head disks, etc., specific locations (home position, word count position, sector position, etc.) are assigned for identification. In characterizing the address indicia, the utilization of a full set of addresses can consume an inordinate portion of storage space or cost.

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Symmetric Partial Addressing

It is common in memory apparatus to store identification or other address indicia with data. In plural channel recording apparatus, such as multi-track tape, fixed head drum or disk, bubble plates, core memories or plural shift registers, one or more of the plurality of channels can be dedicated to addressing or identification. While in serial devices such as single shift registers, delay lines, movable head disks, etc., specific locations (home position, word count position, sector position, etc.) are assigned for identification. In characterizing the address indicia, the utilization of a full set of addresses can consume an inordinate portion of storage space or cost.

The problem of space consumption is exemplified by paper or magnetic tape, where relatively few channels are available. The problem of cost is seen in a movable head disk, with a few dedicated tracks for synchronization and address location. In this latter device, the sensing apparatus related to the dedicated tracks is often intricate and expensive, and precludes assigning enough tracks for full address information.

In accordance with this description, the address is contained in a plurality of channels logically adjacent other channels carrying the data. Described will be storage and interpretation of a single eight-unit symbol address, it being understood that in a plural symbol address, each symbol can be handled independently in accordance with the present description.

Using the described approach, the storage space required for address indicia has been reduced by one third. This is achieved by rearranging the significance of the address bits, and utilizing principles of geometry in achieving complete address determination from a partial address. The geometry selected allows the establishment of a full address from any single channel or from a combination of channels, thereby adding reliability to address sensing.

A full address structure requires three channels for identifying eight channel positions, as shown in the table below: FULL ADDRESS STRUCTURE Channel Position 2/0/ 2/1/ 2/2/ 2/3/ 2/4/ 2/5/ 2/6/ 2/7/ 1st channel 0 0 0 0 1 1 1 1 2nd Channel 0 0 1 1 0 0 1 1 3rd Channel 0 1 0 1 0 1 0 1 Data Channels.

The full address structure for the eight channel positions is permuted, as shown in the below table: PERMUTED FULL ADDRESS Channel Position 2/0/ 2/1/ 2/2/ 2/3/ 2/4/ 2/5/ 2/6/ 2/7/ 1st Channel 0 0 0 1 0 1 1 1 2nd Channel 0 0 1 0 1 1 1 0 3rd Channel 0 1 0 1 1 1 0 0 Data Channels.

Taking the permuted full address and deleting the second channel, a partial symmetric address is achieved as shown below:. PARTIAL SYMMETRIC ADDRESS Channel Position 2/0/ 2/1/ 2/2/ 2/5/ 2/3/ 2/7/ 2/6/ 2/4/ 1st Channel 0 0 0 1 0 1 1 1 3rd Channel 0 1 0 1 1 1 0 0 Data Channels.

There is nothing special about deleting the second channel; any one or two channels can be deleted.

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The geometric relationships between the partial address bits in each...