Browse Prior Art Database

FET Hall Transducer With Control Gates

IP.com Disclosure Number: IPCOM000082426D
Original Publication Date: 1974-Dec-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Braun, RJ: AUTHOR [+3]

Abstract

It is desirable to have a Hall cell that has a control or compensation technique, high-magnetic sensitivity with respect to current flow in the cell, a minimum temperature sensitivity, and be compatible with an integrated circuit (IC) technology.

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FET Hall Transducer With Control Gates

It is desirable to have a Hall cell that has a control or compensation technique, high-magnetic sensitivity with respect to current flow in the cell, a minimum temperature sensitivity, and be compatible with an integrated circuit (IC) technology.

The field-effect transistor (FET) Hall cell with a control gate offers these advantages. It is constructed using the metal-oxide semiconductor (MOS) system with either an N or P channel. For an N-type Hall cell, constructed on a P-type substrate, the source, drain, and Hall contacts and #2 are N++ diffusions. Both the control and main gates are metal deposited on the silicon dioxide insulating layer. The control gate is insulated from the main gate and although only one control gate is shown, multigates can be used.

The basic operation is the same as MOSFET structures with the inversion layer formed by applying a potential to the main gate. The difference is that the smaller control gate can be used to redistribute the inversion charge layer in such a way, that a potential difference between Hall electrodes #1 and #2 will be created. This redistribution in the channel is produced by applying a potential that is either larger or smaller than the main gate potential to the control gate.

The potential difference caused by the control gate is used to eliminate offset voltages, introduce a predetermined Hall voltage, create a hysteresis for switching uses, introduce negative feedback, et...