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Frequency Monitoring Circuit

IP.com Disclosure Number: IPCOM000082437D
Original Publication Date: 1974-Dec-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 61K

Publishing Venue

IBM

Related People

Pilkington, RE: AUTHOR

Abstract

The circuit shown in Fig. 1 provides a monitoring circuit for accurately monitoring the frequency of pulse trains, especially for monitoring the frequency of pulses generated by a transducer coupled to a document transport.

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Frequency Monitoring Circuit

The circuit shown in Fig. 1 provides a monitoring circuit for accurately monitoring the frequency of pulse trains, especially for monitoring the frequency of pulses generated by a transducer coupled to a document transport.

The emitter transducer output on a line 3 is supplied to a set of two J-K master-slave flip-flops 5 and 7. Clock pulses on a line T2 are supplied to flip-flop 7 from a free-running clock 9 having outputs T0, T1 and T2, having a sequential relation shown in Fig. 2. The clocking pulses occur at a frequency much greater than the nominal frequency of the emitter transducer pulses. Use of the cascaded J-K triggers will provide one and one only series of the timing pulses T0, T1 and T2 within each "emitter" pulse appearing at line 11, the output of trigger 7.

A clock cycle counter 13 is driven by a pulse T0 from the clock 9, and in conjunction with a "good" emitter counter 15 driven by emitter pulses on line 11, is used to determine when a predetermined number of successive "up to speed" emitter pulses on line 11 has occurred, as determined by a "decode Z" circuit 17, the output of which turns on the "up to speed" trigger 19, thereby providing an "up to speed" signal on line 21.

The good emitter counter 15 is reset by each T1 clock pulse supplied to AND circuit 23 until the run condition line 25 is turned on, whereupon the signal supplied to AND 23 via OR 27 and inverter 29 is removed, disabling AND 23. At this time, the clock cycle counter 13 is set on with each TO pulse, but is then reset for each T2 pulse, which is passed by an AND circuit 31, enabled by an output from OR 33 which is supplied from the decode "0" circuit 35 connected to the outputs of the good emitter counter 15.

When the run condition signal line 25 is brought up, the associated document transport is started and the first emitter pulse rises and falls, causing the first stage of the good emitter counter 15 to turn on. Accordingly, decode 0 circuit 35 is turned off, and the reset signal is removed from the clock cycle counter 13, thereby allowing it to advance on the fall of each successive T0 pulse.

The outputs of the clock cycle counter 13 are supplied to three decoding circuits 37, 39...