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Circuit Change Indicator

IP.com Disclosure Number: IPCOM000082441D
Original Publication Date: 1974-Dec-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 49K

Publishing Venue

IBM

Related People

Britt, RF: AUTHOR

Abstract

Shift registers are wired together in an order dictated by the geometry of the circuit placement on semiconductor chips and the chip placement within the module, rather than the functional use of the latches. External tables are required to reorder the bits into a functional or "logical" order.

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Circuit Change Indicator

Shift registers are wired together in an order dictated by the geometry of the circuit placement on semiconductor chips and the chip placement within the module, rather than the functional use of the latches. External tables are required to reorder the bits into a functional or "logical" order.

For proper operation, it is extremely important that the external tables are properly matched to the design or engineering change (EC) level of the module. Certain knowledge of EC levels is also vital to error-analysis algorithms, repair verification, testing procedures, proper installation of features, and other normal activities. Hence, a direct read-out of the EC level of large-scale integration (LSI) modules is advantageous and highly desirable.

When ECs are made to a module, only one or two chips (out of 100) are modified. This has made it impractical to hard-wire an EC level indicator into the module, because that would require the hard-wired chips to also be modified, doubling the cost of an EC.

The present arrangement allows the hard-wiring to occur only on the chips modified by the EC, resulting in a predictable, recognizable pattern that can be translated into an EC level. It consists primarily of a single-wire bus 3 (EC bus) that is distributed to (or run serially through) each chip 5 within the module 7. The bus is controlled externally from the module, through the maintenance interface provided to operate the shift registers and clocks. For the initial design, the bus is not connected to any of the shift register latches in the module.

During the design of an EC which affects one or more chips, one arbitrarily selected existing latch on any or all of the affected chips is...