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Microword Bit Overlap of the Next Address Field

IP.com Disclosure Number: IPCOM000082447D
Original Publication Date: 1974-Dec-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 71K

Publishing Venue

IBM

Related People

Johnson, AM: AUTHOR

Abstract

A technique is described which increases the number of microword functions which are available in one or more word types of a processor, without increasing the number of logical bits required in the microword. It is frequently difficult during the design of a new processor to encode all of the required-machine functions into a microword set, because the number of logical bits in the microword is restricted. Typically the machine designer incorporates as much function and performance into the microword set as is possible, without increasing the number of bits. Thus, a compromise is frequently made between word size and function capability. As a result, many of the functions which are desired do not get implemented.

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Microword Bit Overlap of the Next Address Field

A technique is described which increases the number of microword functions which are available in one or more word types of a processor, without increasing the number of logical bits required in the microword. It is frequently difficult during the design of a new processor to encode all of the required-machine functions into a microword set, because the number of logical bits in the microword is restricted. Typically the machine designer incorporates as much function and performance into the microword set as is possible, without increasing the number of bits. Thus, a compromise is frequently made between word size and function capability. As a result, many of the functions which are desired do not get implemented.

Fig. 1 illustrates a microprogram controlled processor generally of the type shown and described in detail in U. S. Patent 3,648,246. The processor includes a control register C which holds microprogram control words during their execution. Fig. 1 illustrates typical control fields in an arithmetic type microword, together with various components of the processor which are controlled by the respective fields, i.e., A and B local stores 5, 6; A and B address decode circuits 150, 151; P, A, B and Z registers 7a, 21, 22, 30; main control store address register 112; A and B assemblers 23, 24; and ALU2 and ALU3.

The technique illustrated by Fig. 1 provides additional functions for the byte add arithmetic word type, which functions would normally require more than the thirty-two logical bits shown. This is achieved by overlapping one or more of the next address bits with a corresponding number of bits that perform an entirely different function. By way of example, the higher order branch bit C3.5 (byte 3, bit 5) is also used as the low-order next address bit. This means that bit C3.5 is used simultaneously to perform two completely independent functions, i.e., the next address gating circuits 1 and the branch decode circuits 2 both respond to the common bit C3.5.

The low-order bit C3.5 in the next address field can be shared with fields other than the branch field. The choice of the field which...