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Troubleshooting Large Scale Integrated Circuit Units

IP.com Disclosure Number: IPCOM000082448D
Original Publication Date: 1974-Dec-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 4 page(s) / 69K

Publishing Venue

IBM

Related People

Howe, LD: AUTHOR [+2]

Abstract

This method enables the troubleshooting of inaccessible data processing circuits buried within a large-scale integrated circuit (LSI) package, in a manner having a flexibility and utility which is comparable to the troubleshooting of nonintegrated circuits with an oscilloscope and test probe. This is accomplished by including within the LSI package various buffer latch circuits for sampling the signal values in significant ones of the data handling circuits and scanning mechanisms for scanning out the sampled data values, and by providing circuitry for operating the buffer latches so as to be able to look at or sample signal conditions at different points in time during the operating cycles of the data handling circuits.

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Troubleshooting Large Scale Integrated Circuit Units

This method enables the troubleshooting of inaccessible data processing circuits buried within a large-scale integrated circuit (LSI) package, in a manner having a flexibility and utility which is comparable to the troubleshooting of nonintegrated circuits with an oscilloscope and test probe. This is accomplished by including within the LSI package various buffer latch circuits for sampling the signal values in significant ones of the data handling circuits and scanning mechanisms for scanning out the sampled data values, and by providing circuitry for operating the buffer latches so as to be able to look at or sample signal conditions at different points in time during the operating cycles of the data handling circuits.

The figure shows an example of how this troubleshooting method may be implemented. This troubleshooting method is particularly useful in connection with LSI modules which contain large numbers of integrated circuit chips each of which, in turn, has a large number of data processing circuits formed thereon. A typical module may include, for example, various multibit data registers; shift registers, arithmetic and logic circuits, and the like.

In the figure, boundary line 110represents the boundary of a typical LSI module, while boundary line 11 represents the boundary of a typical integrated circuit chip within such module 10. Located on the chip 11 is a typical type of data processing circuitry in the form of an eight-bit data register 12. As such, register 12 includes eight latch stages 13-20, with stages 16-18 and parts of stages 15 and 19 being omitted for simplicity of illustration.

Each of the register stages 13-2O includes a data latch circuit for receiving a data bit from some other data processing unit and a buffer latch circuit (BFR) for use in connection with the troubleshooting method. Each data latch and each buffer latch is of the two-polarity hold type. The read in and transfer of-data to the register stages 13-20 is controlled by appropriate signals on conductors S, A and
B. Conductor S is used for normal register read in purposes, which conductors A and B are used for troubleshooting type scanout purposes.

Considering in detail, for example, the register stage 14, the presence of an enabling signal on conductor S will cause the data on data input conductor 21 to be read into and held in the data latch circuit 14a. This data value then appears on the data output conductor 22. The presence of an enabling signal on conductor A, causes the data value on conductor 23 coming from the preceding stage 13 to be read into and held in the data latch circuit 14a. The presence of an enabling signal on conductor B causes the data value currently held in the data circuit 14a to be read into and held by the buffer latch circuit 14b, the circuit connection being internal and not appearing on the drawing. The data value being held by the buffer latch circuit 14b a...