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Browse Prior Art Database

Densified Wiring Channels Design Concept

IP.com Disclosure Number: IPCOM000082459D
Original Publication Date: 1974-Dec-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Balyoz, J: AUTHOR [+2]

Abstract

The first and the second level interconnecting metal conductors on large-scale integrated (LSI) chips are designed on a closer channel grid, by using minimum metal-to-metal spacing and off-centered and oriented via pads. This concept yields greater density of conductors and a substantial area savings on LSI chips with multilevels of metallization.

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Densified Wiring Channels Design Concept

The first and the second level interconnecting metal conductors on large- scale integrated (LSI) chips are designed on a closer channel grid, by using minimum metal-to-metal spacing and off-centered and oriented via pads. This concept yields greater density of conductors and a substantial area savings on LSI chips with multilevels of metallization.

The drawing depicts only a small portion of an LSI chip surface. A densely wired area between the two adjacent conductors 10 and 20, channel grid spacing 30, is determined by the metal-to-metal spacing rather than the spacing between a via pad such as 40 and a metal conductor. Where a via pad 50 or 80 is placed, the adjacent conductor channels 60 or 90 are interrupted. However, these conductor channels are still useful for placing conductors 70 or 100.

Vias designated with a (V), such as 45, interconnect metal paths between two levels of metal conductors, separated by an insulating layer. Vias designated with a (P) such as 115 interconnect with an input output pin of a circuit. Pin pads such as 110 are designed concentrically with the conductors connected thereto. Pin pads may also be placed off-center for further area saving on the LSI chip.

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