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Dynamic Logic Driver

IP.com Disclosure Number: IPCOM000082476D
Original Publication Date: 1974-Dec-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Long, GB: AUTHOR [+3]

Abstract

The circuit 40 is an application of bootstrap type bias to dynamic logic, which allows insertion of a power amplifier between dynamic logic circuits 10 and 30 without a clock phase of delay. Because field-effect transistor (FET) 45 and FET 43 are driven by phase clocks to only provide an up binary level at phase three, each of a plurality of driver circuits 30 may omit the usual transmission FET connected in series between the switching device such as FET 33 and ground reference potential.

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Dynamic Logic Driver

The circuit 40 is an application of bootstrap type bias to dynamic logic, which allows insertion of a power amplifier between dynamic logic circuits 10 and 30 without a clock phase of delay. Because field-effect transistor (FET) 45 and FET 43 are driven by phase clocks to only provide an up binary level at phase three, each of a plurality of driver circuits 30 may omit the usual transmission FET connected in series between the switching device such as FET 33 and ground reference potential.

During phase one, FET 15 unconditionally precharges node 46 and capacitor 44 through FET 45. The phase three clock connection to the drain of FET 45 will be at ground reference potential during phase one clock time. During phase two, FET 35 precharges the output nodes of circuits 30 and FET 41 is conductive to remove any charge from node 48, which may be coupled through intrinsic device capacitance from the output nodes of circuits 30. Also FET 11 and 13 conditionally discharge node 46 and capacitor 44 again through FET 45, if a binary up level is present at signal input A. If node 46 is not discharged, FET 45 is rendered conductive by the charge on capacitor 44, which is additive with the voltage swing of node 48.

Thus, if the phase voltage swings are 0 to 9 volts, the threshold voltage of FET 15 will be negligible while charging capacitor 44 and node 46 remains approximately 5 volts above node 48 as FET 45 turns on at phase three time, raising node 46 to...