Browse Prior Art Database

Integrated Circuit Chip Package

IP.com Disclosure Number: IPCOM000082490D
Original Publication Date: 1974-Dec-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Liu, CN: AUTHOR [+3]

Abstract

An integrated circuit chip or wafer package structure is described which permits packaging a plurality of semiconductor chips or wafers on the same substrate, while reducing the adverse affects of different coefficients of thermal expansion between the chip and the substrate.

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Integrated Circuit Chip Package

An integrated circuit chip or wafer package structure is described which permits packaging a plurality of semiconductor chips or wafers on the same substrate, while reducing the adverse affects of different coefficients of thermal expansion between the chip and the substrate.

The figure shows a substrate 1 having a first coefficient of thermal expansion upon which is attached the rigid pedestal 2. Mounted on top of the rigid pedestal 2 is the semiconductor wafer 3. Wafer 6 is mounted on top of wafers 3 by the solder ball joints 7 and 8, which transfer a mechanical moment from wafer 6 to wafer 3 in a cantilever fashion. Electrical contact between the substrate 1 and the wafer 3 is made by wire bond 4. The cantilever suspension for the wafer 3 reduces many of the thermally induced stresses imposed by prior art packaging arrangements.

The cantilever structure can serve as the base for a stacked configuration of semiconductor chips 5 as is shown. Two or more cantilever structures can serve as the base upon which a plurality of integrated circuit chips can be stacked. In an alternative configuration, the semiconductor wafer 3 can be annular in shape and make use of a plurality of rigid pedestals 2 to support the stacked configuration of chips 5 shown in the figure, which will be resistive to thermally induced stresses.

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