Browse Prior Art Database

Testing LSI Memory Arrays Using On Chip I/O Shift Register Latches

IP.com Disclosure Number: IPCOM000082491D
Original Publication Date: 1974-Dec-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Balasubramanian, PS: AUTHOR [+4]

Abstract

Described is a technique for efficiently using the available surface area on a large-scale integrated (LSI) circuit memory array chip, by employing the I/O shift register latches as an on-chip functional testing structure to perform level sensitive scanning of the array during the functional testing of the device.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 69% of the total text.

Page 1 of 2

Testing LSI Memory Arrays Using On Chip I/O Shift Register Latches

Described is a technique for efficiently using the available surface area on a large-scale integrated (LSI) circuit memory array chip, by employing the I/O shift register latches as an on-chip functional testing structure to perform level sensitive scanning of the array during the functional testing of the device.

USP 3,815,025 discloses a level sensitive scan design for large-scale integrated circuit chips. The design includes a shift register to be used during the course of functionally testing the chip. The described circuit makes the modification that a separate testing shift register need not be constructed on the chip, but that the I/O shift register latches which perform the I/O function for the memory array during its normal operation, can be connected to also serve as the testing shift register during the functional testing of the LSI device.

Fig. 1 shows a shift register latch which is suitable for use, both as the I/O latch for the LS1 memory array and as one stage in the shift register to be employed in a level sensitive scan design. During testing, three clock signals are required to operate the shift register latch; the A shift clock, the B shift clock, and the "C" data clock signals. The "C" data clock signal regulates the parallel in - parallel out data of L1, the input data clock "C" equaling the ROS/RAM reset clock and the output data clock "C" equaling the ROS/RAM chip select cl...