Browse Prior Art Database

Modified Weinberger Chip Image for Improved Density of Depletion Load FET Circuits

IP.com Disclosure Number: IPCOM000082492D
Original Publication Date: 1974-Dec-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Love, RD: AUTHOR

Abstract

A circuit layout is described which permits multiple circuits to share the same horizontal wiring channel, without requiring extra channels for each load device.

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Modified Weinberger Chip Image for Improved Density of Depletion Load FET Circuits

A circuit layout is described which permits multiple circuits to share the same horizontal wiring channel, without requiring extra channels for each load device.

USP 3,475,621 discloses a standardized high-density integrated circuit arrangement comprising a spaced parallel array of horizontal source and drain diffusions, over which an arrangement of gate metallizations can be placed to form NOR field-effect transistor (FET) logic configurations. Static logic circuits are shown in the patent with a load device oriented, so as to produce a long horizontal output rail from which the circuit output is tapped.

The layout shown in the figure herein, shows three circuits placed across a column with the load devices oriented to allow multiple circuits to be placed across the same horizontal wiring channels. The reorientation of the load devices permits multiple circuits to share the same horizontal wiring channel, without requiring extra channels.

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