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CPU Channel Pulse Synchronization

IP.com Disclosure Number: IPCOM000082499D
Original Publication Date: 1974-Dec-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Unterberger, RM: AUTHOR

Abstract

The synchronization signal between a Central Processing Unit (CPU) and a channel during transfers of data in some models of IBM System/370 is the "address valid" pulse. This control signal can arrive in the CPU asynchronously relative to the CPU clock. This condition has caused signal glitching, bistable pulses, and synchronization problems in the CPU, which due to technology characteristics have never previously been completely resolved, only minimized.

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CPU Channel Pulse Synchronization

The synchronization signal between a Central Processing Unit (CPU) and a channel during transfers of data in some models of IBM System/370 is the "address valid" pulse. This control signal can arrive in the CPU asynchronously relative to the CPU clock. This condition has caused signal glitching, bistable pulses, and synchronization problems in the CPU, which due to technology characteristics have never previously been completely resolved, only minimized.

An approach to resolving this problem is to take advantage of the system characteristics; i.e., the defined delays in generating a channel signal from the receipt of a CPU signal and the cable delay between the channel and the CPU.

The signal generated in the CPU will be activated at the same instant of time (+ or - circuit tolerances) with respect to the CPU clock. The cable delay between the CPU and the channel is a constant. The time of arrival of a CPU signal in the channel to the time of departure of the resultant signal (assuming a constant logic path and circuit tolerances) has a constant period. This resultant signal will arrive in the CPU dependent upon the cable delay between the units; as noted earlier, a constant.

Although the delays mentioned above are relative constants, their total may not necessarily be an integral of the CPU clock; therefore, the resultant pulse may arrive in the CPU at any time relative to the CPU clock. To correct for this inconsistency, a vari...