Browse Prior Art Database

Regulation of Time of Day Clock

IP.com Disclosure Number: IPCOM000082502D
Original Publication Date: 1974-Dec-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 45K

Publishing Venue

IBM

Related People

Duke, KA: AUTHOR

Abstract

The time of day (TOD) clock consists of a counter whose count rate accurately represents the passage of time. It is frequently required to run synchronously with a basic system clock, whose frequency is not maintained to the required precision.

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Regulation of Time of Day Clock

The time of day (TOD) clock consists of a counter whose count rate accurately represents the passage of time. It is frequently required to run synchronously with a basic system clock, whose frequency is not maintained to the required precision.

The TOD clock consists of a counter which is incremented by a fixed amount for each cycle of the system clock. Typically the fixed amount is not a whole number (integer) and fractions are synthesized, by adding the integer above and below the required fraction in the appropriate ratio. For example, if it is required to count to 4096 every microsecond using a 25 mu sec system clock, 102.4 must be added to every cycle. This can be achieved by adding 103 for four out of every ten cycles and 102 for the remainder.

If however, the system clock varies from the nominal 25 mu sec period, the count rate can be maintained by varying the ratio of adding 103 and 102. If the system clock frequency is reduced by 0.1%, the counter must be incremented by 103 for five out of every ten cycles to maintain the same count rate. Fig. 1 shows a way to automatically adjust that ratio.

A convenient carry 10 from the two low-order bytes 11 of the TOD counter to the high-order stages 12, is selected for comparison against a standard. In the above example, the carry after 16 bits (2 bytes) occurs nominally every 16 mu sec. The standard 13 consists of a high-precision oscillator suitably divided down; e.g., a 4 MHz oscillator feeding a 6-bit (divide by 64) counter producing a final carry every 16 mu sec. The two 16 mu sec signals are used to, respectively, reset and set a trigger 14.

The nominal signal from the TOD clock resets the trigger and the standard signal sets it. The trigger is used to determine the count rate, high (103) when set and low (102) when reset. Thus, for a nominal system clock frequency, the 16 mu sec TOD carry from adder 15 should occur two fifths of the period after the standard to maintain the correct count rate.

If the system clock frequency increases, the TOD carry will occur early and will cause the counter to count at the high rate for a shorter period. Similarly, if the system clock frequency decreases, the TOD carry will occur late and cause the counter to count at the high rate for a longer period. Thus, the counter will be adjusted to generate carries at exactly the same rate as the standard, even though running synchronously with an imprecise system clock.

Regulation of the TOD clock to absolute time requires an external standard which is very precisely maintained; as for example, the time signals broadcast by radio station WWV. That standard consists of a series of signals at one second intervals.

In Fig. 2, the 16 mu sec signal is fed into a counter 16 which scales at 62500, and thus generates a reset signal nominally every second. The counter 16 also generates a signal approximately half a second after reset. The one second signal is com...