Browse Prior Art Database

Programmable Priority Mechanism

IP.com Disclosure Number: IPCOM000082505D
Original Publication Date: 1974-Dec-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Christensen, NT: AUTHOR

Abstract

Assigning fixed priority to a set of contending processors is very inflexible. When the processors are identical, and can be doing tasks interchangeably, it is desirable to be able to dynamically set their relative priorities to meet existing requirements.

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Programmable Priority Mechanism

Assigning fixed priority to a set of contending processors is very inflexible. When the processors are identical, and can be doing tasks interchangeably, it is desirable to be able to dynamically set their relative priorities to meet existing requirements.

Assuming that there are N priority levels, N-1 registers are implemented, each large enough to contain the encoded ID of the processors. These registers are written dynamically during system operation with the processor ID's as desired by a supervisor program, machine status, or any other appropriate mechanism, either software or hardware. In general, there are usually the same number of processors as priority levels. However, in the implementation shown it is not necessary that all processors be assigned a priority level.

The figure shows an implementation for a four-processor system. When all processors are assigned different priorities, three ID's are written and the fourth gets lowest priority by default.

It may be desirable to assign priority to, say, just one processor by writing the same ID in all priority registers, or to some subset of the processors, leaving the remainder to be prioritized by a hardware default mechanism. This is also shown in the figure.

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