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Technique for Online Measurement of Chip Delays

IP.com Disclosure Number: IPCOM000082507D
Original Publication Date: 1974-Dec-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Jordan, PV: AUTHOR

Abstract

One of the problems of working with large-scale integration (LSI) technology is the inherently greater effect of delay tolerance on machine performance. This is due to the greater dependence of circuits on one another and the concomitant loss of delay statistics. A technique is shown which allows a relatively simple measurement of the circuit delay on each of the chips on a module. This information can then be used to modify clock distribution in a data processing system and improve the overall machine timing as a result.

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Technique for Online Measurement of Chip Delays

One of the problems of working with large-scale integration (LSI) technology is the inherently greater effect of delay tolerance on machine performance. This is due to the greater dependence of circuits on one another and the concomitant loss of delay statistics. A technique is shown which allows a relatively simple measurement of the circuit delay on each of the chips on a module. This information can then be used to modify clock distribution in a data processing system and improve the overall machine timing as a result.

The structure shown in the figure is typical of chips comprised of combinational logic and a shift register with clock control at the module pins. Generally, the chip shift registers will be interconnected on the module to form one long shift register.

Additional circuitry has been added to this basic structure with gates 1 and 2 to close the loop of the chip shift registers, so that they will recirculate under clock control. To enter this mode, all module scan clocks are enabled and the recirculate line is activated on one of the chips of the module. The selected chip shift register will then recirculate at a frequency which is inversely proportional to the total delay through the shift register and the feedback path, at approximately a 50% duty cycle.

Since all other scan clocks are enabled, the module shift register becomes a transmission gate for the oscillating output of the selected chip. Thus, the frequency can be monitored at the Shift Data Out pin of the module or if many modules are interconnected through their shift registers, the out...