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Field Effect Transistor Driver Circuit

IP.com Disclosure Number: IPCOM000082512D
Original Publication Date: 1974-Dec-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Aoki, T: AUTHOR [+4]

Abstract

The driver circuit shown in the drawing is an improvement on the driver shown in the publication by some of the same authors in the April, 1974 IBM Technical Disclosure Bulletin Vol. 16, No. 11, page 3713. The improved driver circuit has an amplifier stage which supplies a larger voltage swing for the depletion transistor in the output stage, to enhance the power driving capabilities with a lower power dissipation.

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Field Effect Transistor Driver Circuit

The driver circuit shown in the drawing is an improvement on the driver shown in the publication by some of the same authors in the April, 1974 IBM Technical Disclosure Bulletin Vol. 16, No. 11, page 3713. The improved driver circuit has an amplifier stage which supplies a larger voltage swing for the depletion transistor in the output stage, to enhance the power driving capabilities with a lower power dissipation.

In the schematic circuit drawing, an input voltage Vin on a terminal 1 is connected by a conductor 2 to the gate of an enhancement mode field-effect transistor (FET) 3 having its source connected to ground. The drain of FET 3 is connected to the source and gate of a depletion mode FET 4, with its drain supplied with voltage from a supply line 5. The inverted voltage at the source of FET 4 is also applied to the gate of an enhancement mode FET 6 of an output stage. The source of FET 6 is at a ground potential with the drain connected to the source of a depletion mode FET 7 and to an output terminal 8.

An amplifier section 10 is provided to supply the gate drive for transistor 7 and comprises two pairs of FETs. FETs 11 and 12 are enhancement mode and depletion mode, respectively, and are connected in series between the drain source 5 and a source 13 of voltage for the semiconductor substrate in which the FETs are deposited. The gate of transistor 11 is connected to the input conductor 2 and that of FET 12 is connect...