Browse Prior Art Database

# Parity Predict

IP.com Disclosure Number: IPCOM000082513D
Original Publication Date: 1974-Dec-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 46K

IBM

## Related People

Bodner, RE: AUTHOR

## Abstract

A parity predict circuit provides a parity bit for both arithmetic and logic functions of an arithmetic and logic unit (ALU). The predicted parity bit and the generated parity bit from the ALU data bits are compared as an ALU parity check. By forming the predicted parity bit separate from the ALU, the predicted parity bit can be stored with the data earlier than if it had been dependent upon ALU operations.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 69% of the total text.

Page 1 of 2

Parity Predict

A parity predict circuit provides a parity bit for both arithmetic and logic functions of an arithmetic and logic unit (ALU). The predicted parity bit and the generated parity bit from the ALU data bits are compared as an ALU parity check. By forming the predicted parity bit separate from the ALU, the predicted parity bit can be stored with the data earlier than if it had been dependent upon ALU operations.

The hardware design is such that the transmitted carries are used for predicting parity for arithmetic operations. The transmitted carries are blocked during logical operations, and the residual carry is used for predicting parity for logical OR and logical AND operations.

The overall arrangement is shown in Fig. 1 where the operands in registers 10 and 15 are applied simultaneously to ALU 20 and parity predict circuit 25, respectively. The data bits from ALU 20 are used by parity generate circuit 30 to provide a generated parity bit. The predicted parity bit is compared by compare circuit 35 with the generated parity bit, and if there is a lack of comparison, an error is indicated.

The parity predict circuit 25 is shown in detail in Fig. 2. The equations for generating the predicted parity are as follows:

(Image Omitted)

(Image Omitted)

(Image Omitted)

The parity predict circuit 25 includes AND function logic 45 and OR function logic 46 which operate on the bits from registers 10 and 15, to provide AND and OR function inputs into predict logic...