Browse Prior Art Database

Read Write Buffer Control

IP.com Disclosure Number: IPCOM000082526D
Original Publication Date: 1974-Dec-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 53K

Publishing Venue

IBM

Related People

Duggan, CJ: AUTHOR

Abstract

A read/write buffer is controlled in a manner to be read or written by one source asynchronously with a synchronous read being performed by another source. This arrangement finds particular utility for buffering characters to be displayed by a device attached to a computer system, and particularly where the computer system includes microprogramming.

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Read Write Buffer Control

A read/write buffer is controlled in a manner to be read or written by one source asynchronously with a synchronous read being performed by another source. This arrangement finds particular utility for buffering characters to be displayed by a device attached to a computer system, and particularly where the computer system includes microprogramming.

Read/write buffer 10 stores a plurality of characters at predetermined address locations. The characters stored in coded form can be, for example, the characters to be displayed by a device attached to the computer system, not shown. Buffer 10 is operated in either a read or a write mode depending upon the level of the signal on line 11. High or low signal levels on line 11 indicate read or write modes, respectively. Characters are entered into buffer 10 over data buss 12. In order to enter or read a character from buffer 10, a clock pulse is necessary on line 13. The character to be written into or read from buffer 10 is located by an address on bus 14. A character read from buffer 10 is transmitted to the utilization device, such as a display over bus 21.

Address registers 20 and 30 are both capable of addressing buffer 10. In this instance, address register 30 provides the address for a synchronous read operation of buffer 10, and address register 20 provides an address during an asynchronous read or write of buffer 10. Address register 20 is loaded with an address over bus 12 under control of a load signal on line 22. It can be incremented by a signal on line 23 or it can be updated by applying a new address to bus 12. It is reset by a signal applied to line 24. The address in register 20 is gated to buffer 10 by gate 25 via OR circuit 15. Gate 25, however, is conditioned only if buffer 10 is not being addressed by register 30.

The address in register 30 is valid whenever the input conditions of AND circuits 34 or 35 have been satisfied. AND circuit 34 receives a display control signal on line 37, a timing signal RR9 on line 38 and a character timing signal CC3-42 on line 39. The output of AND circuit 34 is applied via 0R circuit 36, to gate 40 and to inverter 41. This causes gate 40 to pass the address from register 30 to buffer 10 via OR circuit 15 and inhibit the passag...