Browse Prior Art Database

Hex Branch

IP.com Disclosure Number: IPCOM000082529D
Original Publication Date: 1974-Dec-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Bodner, RE: AUTHOR [+5]

Abstract

Apparatus is provided for executing a hex branch instruction which enables branching to any of sixteen groups of sixteen words each. An unconditional branch can be taken thereafter to reach a 4000 word field. The contents of a general purpose register are used for the branch. The hex branch instruction is specifically useful for emulation functions and for transferring control into a table of unconditional branches.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 2

Hex Branch

Apparatus is provided for executing a hex branch instruction which enables branching to any of sixteen groups of sixteen words each. An unconditional branch can be taken thereafter to reach a 4000 word field. The contents of a general purpose register are used for the branch. The hex branch instruction is specifically useful for emulation functions and for transferring control into a table of unconditional branches.

The computer system shown in Fig. 1 is a stored program computer where the high-level instructions are executed by an emulator. The hex branch instruction has an operation code of hexadecimal F, as shown in Fig. 3. When the hex branch instruction is retrieved from storage 10, Fig. 1, it is entered into registers 15 and 20 simultaneously. Register 15 is the instruction register and bits 0-3 thereof are decoded by decode logic 16, which generates a hex branch signal upon decoding a hexadecimal F. Bit 12, an operation code extend bit is also decoded. Bit 12 is 0 for a hex branch instruction. This hex branch signal is used for controlling storage gates 25 and ALU gates 40, as seen in Fig. 2.

LSR Select Logic 45 is responsive to bits 5-7 of the hex branch instruction to select a register 51, Fig. 2, contained in a stack of local store registers (LSR's) 50, Fig. 1. The low-order byte (bits 8-15) or the high-order byte (bits 0-7) of register 51 are passed by gates 25 into register 30. Bit 4 of the instruction, if 1 causes the high gates 25 to pass the high-...