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System Initialization Check

IP.com Disclosure Number: IPCOM000082531D
Original Publication Date: 1974-Dec-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 84K

Publishing Venue

IBM

Related People

Bodner, RE: AUTHOR [+3]

Abstract

The system reset signal normally used to set a stored program computer into an initial state, gates logic for detecting and identifying hardware malfunctions in the computer. The computer system is designed in a manner that the system reset signal initializes hardware such as system buses, registers and event indicators to a known state. The inputs and/or outputs of the hardware elements to be tested are logically combined by OR circuits, and the outputs thereof are fed to AND circuits gated by the system reset signal. The outputs of the AND circuits feed event or lamp indicators which had been switched off by the system reset signal. Any malfunction detected by the logical OR and AND circuits switches on the appropriate lamp indicator.

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System Initialization Check

The system reset signal normally used to set a stored program computer into an initial state, gates logic for detecting and identifying hardware malfunctions in the computer. The computer system is designed in a manner that the system reset signal initializes hardware such as system buses, registers and event indicators to a known state. The inputs and/or outputs of the hardware elements to be tested are logically combined by OR circuits, and the outputs thereof are fed to AND circuits gated by the system reset signal. The outputs of the AND circuits feed event or lamp indicators which had been switched off by the system reset signal. Any malfunction detected by the logical OR and AND circuits switches on the appropriate lamp indicator.

In Fig. 1 AND circuits 11, 12, 13 and 14 are conditioned by the output of AND circuit 15. AND circuit 15 passes a conditioning signal during the absence of a system reset signal and the presence of a GATE NORMAL DISPLAY signal. Inverter 16 is responsive to the absence of a system reset signal for conditioning AND circuit 15. Hence, during normal system operation, conditions of displayable hardware are displayed by lamp indicators, not shown, driven by signals via AND circuits 11-14 inclusive and OR circuits 17-20 inclusive.

AND circuits 21-24 inclusive are gated by the system reset signal to detect hardware malfunctions. Malfunctions or defects in data bus 25 are detected by OR circuit 26 and AND circui...