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Diagnose Instruction for Modular Processing System

IP.com Disclosure Number: IPCOM000082544D
Original Publication Date: 1974-Dec-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 61K

Publishing Venue

IBM

Related People

Doty, CR: AUTHOR [+4]

Abstract

Described is a diagnostic facility which unifies manual and program oriented maintenance for the multiprocessor computing system shown in Fig. 1. A multiplicity of computing elements (QUADS 1 and 2) are connected to maintenance console 3, along with other elements such as channels 4, 5 and 6. The maintenance console 3 can exercise any of the system resources to which it is connected. These resources each have paths back to the maintenance console 3, and the maintenance console 3 serves as a communication link between the system resources.

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Diagnose Instruction for Modular Processing System

Described is a diagnostic facility which unifies manual and program oriented maintenance for the multiprocessor computing system shown in Fig. 1. A multiplicity of computing elements (QUADS 1 and 2) are connected to maintenance console 3, along with other elements such as channels 4, 5 and 6. The maintenance console 3 can exercise any of the system resources to which it is connected. These resources each have paths back to the maintenance console 3, and the maintenance console 3 serves as a communication link between the system resources.

By defining a common core of maintenance control logic in the maintenance console 3 to serve QUADS 1 and 2, a diagnostic bridge between processors can be achieved making it possible for one processor to control and analyze malfunctioning in its neighbor.

The format of the DIAGNOSE instruction is shown in Fig. 2. It has a privileged OP code and is valid only in the supervisor mode. The I-field specifies the operand format for four types of operations defined for the DIAGNOSE instruction. The four types of operation are code 00, diagnose No-OP, code 01, for setting the maintenance console address register (MCAR) and the cycle counter (CPC) count, code 10 for setting the maintenance console data register (MCDR) with data, and code 11, for setting the status control word (SCW) and the console maintenance word (CMW).

The B and D fields are combined to form a 16-bit address which is used to fetch a double word (operand) from main storage for loading various hardware registers or activating certain MC switch functions for the main processor.

Fig. 3 illustrates the data flow of the DIAGNOSE instruction. When the DIAGNOSE OP code is encountered during normal instruction processing, the I- field is held in the I-unit execution register (E-REG-20) and the pipeline is drained. The diagnose operand is fetched from main storage into G-REG 10. Upon the fetch return, the operand is loaded into the maintenance console staging register (MCSR) 30 over the maintenance console data bus in (MCDBI) and the I-unit enters a STOP state.

The MC assumes control and decodes the DIAGNOSE I-field being held in the I-unit E-REG 20 via decode 40. If the decoded operation is code 00, the MC sends the diagnose release signal to the I-unit and instruction processing resumes. The maintenance mode register (MMR) containing the SCW, the...