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Ungated Field Effect Transistor Memory Cell

IP.com Disclosure Number: IPCOM000082582D
Original Publication Date: 1975-Jan-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 38K

Publishing Venue

IBM

Related People

Chang, WH: AUTHOR [+2]

Abstract

This single-device dynamic memory cell is fabricated by standard field-effect transistor (FET) processing and provides increased performance over FET memory cells, in view of its use of subsurface current.

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Ungated Field Effect Transistor Memory Cell

This single-device dynamic memory cell is fabricated by standard field-effect transistor (FET) processing and provides increased performance over FET memory cells, in view of its use of subsurface current.

Fig. 1 shows an ungated FET and Fig. 2 its electrical characteristics. The drain current IDs is 0 before VDS reaches punch-through voltage PT. After punch-through is reached, the current increases exponentially at first, and then levels off approximately as a function of (VD-PT)/2/ at high current. The punch- through voltage is a function of a substrate bias, source-to-drain diffusion and bulk semiconductor doping density. By making the channel length short or the substrate doping density low, PT may be established at a relatively low value.

Fig. 3 shows a pair of dynamic memory cells which utilize the punch-through phenomena. Using, for example, a P-type semiconductor wafer 10, longitudinal N+ diffused bit-sense lines B/S1 and B/S2 are provided. Adjacent to each B/S line there are a plurality of Isolated N+ diffusion pockets DP1 and DP2 which act as charge storage nodes. Overlying the surface of wafer 10 is an insulating layer 12, which includes thin portions adjacent to each diffusion pocket DP. Parallel conductive metal or polysilicon word lines W/L, associated with one diffusion pocket DP of each bit sense line, are provided to manipulate the voltage on the diffusion pockets.

Isolation between cells is provided by a larger separation between diffusion pockets of different memory cells, that between B/S lines and associated diffusion pockets DP. Other isolation methods such as diffused P+ pockets, recessed oxide or surface ion implantation may be used to increase the cell density. An ohmic contact is provided to the wafer 10 to enable application of substrate voltage Vsub.

Assuming, for example, that 0 voltage on a diffusion pocket DP represents a logical 0 and a +5 volt potential on a diffusion pocket represents a logical 1 and that a punch-through vo...