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Integrated Binary Power Controller

IP.com Disclosure Number: IPCOM000082585D
Original Publication Date: 1975-Jan-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 40K

Publishing Venue

IBM

Related People

DeBrita, AA: AUTHOR [+4]

Abstract

Conventional power controllers use analog circuit techniques for control and power regulation. This circuit uses binary logic techniques for power regulation and control and is fabricated in large-scale integration (LSI) technology. In terms of circuit sensitivity, turning a transistor `on' or `off', in a binary system is considerably easier than biasing the same transistor in the linear or the analog region.

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Integrated Binary Power Controller

Conventional power controllers use analog circuit techniques for control and power regulation. This circuit uses binary logic techniques for power regulation and control and is fabricated in large-scale integration (LSI) technology. In terms of circuit sensitivity, turning a transistor `on' or `off', in a binary system is considerably easier than biasing the same transistor in the linear or the analog region.

The figure shows a block diagram of the binary power controller. Counter 1 is an N-stage binary up/down counter used to provide a binary reference number. Counter 2 is an N-stage binary counter operated in continuous up count mode at the master clock frequency, typically 25 megahertz. The compare block is an N- stage comparator, used to determine if the number in counter 2 is equal to, greater than or less than the number in reference counter 1.

Assuming for example that N equals 8, at t = 0, arbitrarily defined as the time when counter 2 is reset from 11111111 to zero, a trigger pulse is supplied to the set input of a binary latch 8. The latch remains set until the number in counter 2 is equal to the number in reference counter 1, at which time the compare gate triggers the reset input of the binary latch 8. Thus the pulse width of the latch output is controlled by the binary number stored in counter 1, in increments of the master clock cycle time.

The cycle time of the latch output is equal to the master clock frequency divided by 2 . The latch output drives a DC-to-DC converter, or series switching regulator 10 which is connected through a filter 12 to the load to be regulated. Filtered output voltage is fed back to a reference detector 14, a slope detector 16, and a coarse rate detector 18.

Reference detector 14 determines if the output voltage is high or low compared to a fixed reference voltage 20. The reference may be a simple center tap of an external potentiometer.

The output of reference detector 14 is a logic level which equals 1 if the output is high and 0 if low. Slope detector 16 provides a logical 1, if the slope of the output voltage is positive and a logical 0 if the slope is negative. Coarse rate detector 18 provides a logical 1 when the magnitude of the output voltage rate of change exceeds the fixed value, for example, 5 millivolts per microsecond, and a logical 0 when the rate is less than the fixed value....