Browse Prior Art Database

High Performance Enhancement Mode FET Logic

IP.com Disclosure Number: IPCOM000082586D
Original Publication Date: 1975-Jan-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Related People

Kruggel, RH: AUTHOR

Abstract

This bootstrap inverter/driver circuit provides an improvement in power/ performance over conventional enhancement mode logic, without the processing complexity of providing depletion load devices. Improvement in linear characteristics and faster transient response are achieved, by operating the driver load device primarily in the triode region as opposed to the saturation region.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 98% of the total text.

Page 1 of 2

High Performance Enhancement Mode FET Logic

This bootstrap inverter/driver circuit provides an improvement in power/ performance over conventional enhancement mode logic, without the processing complexity of providing depletion load devices. Improvement in linear characteristics and faster transient response are achieved, by operating the driver load device primarily in the triode region as opposed to the saturation region.

Metal-oxide semiconductor fields effect transistor (MOSFET) devices T1, T2 and T3 correspond functionally to a conventional bootstrap inverter/ driver. When Vin is a logical 1, capacitive load CL is discharged and T3 precharges node A to a potential one threshold drop below the potential on the gate of T3.

In order to provide accurate control over the potential at the gate of T3, an on chip bias generator comprising T4, T5 and T6 acting as a device parameter dependent voltage divider is provided between VH and Vref. The voltage at node B will be Vref plus the threshold drops across T4 and T5.

Since all the devices are on the same semiconductor chip, threshold voltages of T1, T3, T4 and T5 can be substantially equal. The voltage at node A will charge to Vref + 1 threshold drop. T1 remains above pinch-off until Vout = VLsVref, a threshold independent value. Variations in actual device thresholds from chips to chip will have little effect on power, allowing an improved power/performance product for this design.

1

Page 2 of 2

2

[This page contains...