Browse Prior Art Database

Parity Predictor for Leading Zero Digit Counter

IP.com Disclosure Number: IPCOM000082590D
Original Publication Date: 1975-Jan-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Jeremiah, TL: AUTHOR

Abstract

Fig. 1 shows an 8-byte ALU 1 which performs arithmetic directly on binary and binary-coded decimal data. A hardware counter 2 detects on the ALU output the number of hexadecimal zero digits to the left of significant data, e.g., a nonnormalized floating-point number with zero high-order hexadecimal fraction digits. The counter can be implemented in combinational logic with three-stage delays, and provides a binary count of the number of leading zero digits to the shifter hardware 3 for calculating shift amounts.

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Parity Predictor for Leading Zero Digit Counter

Fig. 1 shows an 8-byte ALU 1 which performs arithmetic directly on binary and binary-coded decimal data. A hardware counter 2 detects on the ALU output the number of hexadecimal zero digits to the left of significant data, e.g., a nonnormalized floating-point number with zero high-order hexadecimal fraction digits. The counter can be implemented in combinational logic with three-stage delays, and provides a binary count of the number of leading zero digits to the shifter hardware 3 for calculating shift amounts.

This arrangement concerns itself with providing for the checking of counter 2 and the data path from counter 2 to shifter hardware 3. The solution to these two problems is to develop a parity bit P for the counter outputs that is independent of the counter hardware 2. The P bit is developed in predictor circuit 4 in the same number of logic block delays as the counter output, so that the parity and counter output bits are available simultaneously. Fig. 2 illustrates the logic for the counter 2 and the parity predictor 4. A "0" on the status register output indicates that its corresponding ALU output digit is a hexadecimal zero, while a "1" indicates a nonzero output digit. "X" is a DON'T CARE.

It is contemplated that the shifting, if any, of data which is emanating from the ALU will occur most of the time during the next processor cycle. Because of the logic delays in the status circuits and in the counter a...