Browse Prior Art Database

Dual Gate FAMOS Memory Cell

IP.com Disclosure Number: IPCOM000082605D
Original Publication Date: 1975-Jan-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

DasGupta, S: AUTHOR [+2]

Abstract

This nonvolatile memory cell has a dual-gate structure. The illustrated structure permits the use of one device per cell, has X-Y select capability, and requires less power during write/erase operation, because the grounded access gate prevents channel current from flowing.

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Dual Gate FAMOS Memory Cell

This nonvolatile memory cell has a dual-gate structure. The illustrated structure permits the use of one device per cell, has X-Y select capability, and requires less power during write/erase operation, because the grounded access gate prevents channel current from flowing.

The device fabricated on substrate 10 has a source 12 and drain 14, a polysilicon floating gate 16, a polysilicon access gate 18, and a write/erase gate 2O. The access gate 18 is used in combination with the drain 14 to provide an X-Y select. The access gate 18 is grounded to prevent channel current from flowing during the write and erase operations. The write/erase gate 20 is biased plus, or minus, to cause electrons or holes to be injected into the floating gate 16 when the drain junction is avalanched. An ion implant, not shown, is done at the drain perimeter under part of the floating gate 16 to reduce the avalanche breakdown voltage.

In a write operation, the access gate 18 is grounded, the control gate 20 biased positively and the drain 14 avalanched. Electrons are introduced into the floating gate 16 to induce a semipermanent charge. In an erase operation, the gate 20 is biased negatively and the drain 14 avalanched, to introduce holes into the polysilicon floating gate 16 to neutralize electrons. The read operation is performed in the conventional manner.

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