Browse Prior Art Database

Safely Exposing Chip Surfaces for Failure Analysis

IP.com Disclosure Number: IPCOM000082625D
Original Publication Date: 1975-Jan-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Bedetti, FV: AUTHOR [+3]

Abstract

This is a technique for safely exposing a plastic-encapsulated integrated circuit (IC) surface without washing away corrosion residues on the chip surface, as is sometimes the case with a wet chemical dissolution process.

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Safely Exposing Chip Surfaces for Failure Analysis

This is a technique for safely exposing a plastic-encapsulated integrated circuit (IC) surface without washing away corrosion residues on the chip surface, as is sometimes the case with a wet chemical dissolution process.

Fig. 1 shows a plastic encapsulated IC 4 mounted on a lead frame 6. In Fig. 2, the plastic from the module's top surface is ground to within a few mils using coarse (180 grit), and then progressively finer silicon carbide grinding discs on standard metallurgical polishing wheels.

In Fig. 3, the remaining plastic on the module's surface is ashed, by exposing the module to a low-temperature oxygen plasma for approximately 30 minutes at 25 watts of RF power. The ash is blown off using a nitrogen or dry air blast. Fig. 4 shows the exposed chip surface.

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