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Electrically Erasable Floating Gate Field Effect Transistor Memory Cell

IP.com Disclosure Number: IPCOM000082628D
Original Publication Date: 1975-Jan-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 54K

Publishing Venue

IBM

Related People

Anantha, NG: AUTHOR [+3]

Abstract

This floating gate avalanche injection field-effect transistor memory cell is adapted to P-channel and N-channel operation, can be electrically erased, and is relatively fast with respect to reading, writing and erasing operations.

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Electrically Erasable Floating Gate Field Effect Transistor Memory Cell

This floating gate avalanche injection field-effect transistor memory cell is adapted to P-channel and N-channel operation, can be electrically erased, and is relatively fast with respect to reading, writing and erasing operations.

The memory cell, illustrated in Figs. 1, 2 and 3, is fabricated on a monocrystalline semiconductor substrate 12, provided with a source 14 and drain region 16. Substrate 12 can have a background doping of a P-type impurity as illustrated, or in the alternative, an N-type. Regions 14 and 16 are formed of an impurity of an opposite type to that of the substrate background impurity.

An insulating layer 18 is provided on the surface of substrate 12 having a greater thickness over the field regions than over the channel region 20. Layer 22, preferably of SiO(2), having a thickness on the order of 250-500 angstroms, is provided between the floating gate 24 and channel 20. An insulating layer 26 overlies gate 24 and is preferably a layer of them all SiO(2), formed by oxidizing the polysilicon gate 24. The thickness of layer 26 is preferably on the order of 1,000 angstroms. A control gate 28, preferably formed of aluminum or other suitable metal, overlies floating gate 24.

Electrical contacts 30 and 32 are provided which form an ohmic contact to source and drain regions 14 and 16. Region 40, shown in Figs. 1 and 3 and formed of the same type dopant as the semiconductor substrate 12, is provided adjacent and in contacting relation to drain region 16. This region is provided to adjust the voltage necessary to cause avalanching of the drain 16 to a lower figure than the avalanching breakdown voltage, required for forming the avalanche condition between the PN junction between substrate 12 and source region 14.

In general, the impurity concentration in region 40 is less than the impurity concentration in drain region 16. The floating gate electrode 24 has a portion 25 that overlies region 40. The control electrode 28 overlies portion 25 and region
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