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Nonvolatile Memory Array with a Single FAMOS Device per Cell

IP.com Disclosure Number: IPCOM000082629D
Original Publication Date: 1975-Jan-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Dockerty, RC: AUTHOR

Abstract

Floating gate avalanche field-effect transistor devices are nonvolatile memory units. In general, a charge is formed on a floating gate disposed over the channel region between the source and drain by avalanching the drain region, and simultaneously applying a negative voltage to a conductive gate over the floating gate. This causes holes formed by the impact ionization phenomenon to penetrate the dielectric layer and lodge in the floating gate, creating a conductive channel between the source and drain regions.

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Nonvolatile Memory Array with a Single FAMOS Device per Cell

Floating gate avalanche field-effect transistor devices are nonvolatile memory units. In general, a charge is formed on a floating gate disposed over the channel region between the source and drain by avalanching the drain region, and simultaneously applying a negative voltage to a conductive gate over the floating gate. This causes holes formed by the impact ionization phenomenon to penetrate the dielectric layer and lodge in the floating gate, creating a conductive channel between the source and drain regions.

The charge can be erased by again avalanching the drain and applying a positive voltage to the conductive electrode over the floating gate, to selectively introduce the opposite type charges into the floating gate to neutralize the previously introduced charges.

In this matrix, a single floating gate avalanche field-effect transistor 10 is provided in each cell. Two word lines 12 and 14 and a single bit line 16 are associated with each column of devices. Line 18 is connected to the substrate of each device cell in a column of cells. The substrate of each column of cells is electrically isolated from adjacent substrate regions.

In a write operation for introducing a charge on the floating gate 20 of cell 1, a voltage BV/2 is applied to line 14 while a negative voltage -BV/2 is applied to line 18 causing avalanching of the drain. BV is the breakdown voltage of the drain. Simultaneously, a negative...