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Computer Controlled Breakdown Voltage Tester for Semiconductor Devices

IP.com Disclosure Number: IPCOM000082658D
Original Publication Date: 1975-Jan-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 3 page(s) / 41K

Publishing Venue

IBM

Related People

Davis, J: AUTHOR [+2]

Abstract

An apparatus is described for automatically testing for the breakdown voltage of a semiconductor device, and provides the numerical value for the breakdown voltage as a digital output.

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Computer Controlled Breakdown Voltage Tester for Semiconductor Devices

An apparatus is described for automatically testing for the breakdown voltage of a semiconductor device, and provides the numerical value for the breakdown voltage as a digital output.

Fig. 1 shows a system block diagram for the apparatus. The test is initiated by the computer command signal shown on the Fig. 2, which is input on line 1 to the counter 4, from the host processor which may be an IBM System 7. The oscillator 2 generates the pulse waveform shown in Fig. 3a, that is transmitted by the AND gate 3, which causes the counter 4 to digitally increment starting with the value 1. The digital values counted by the counter 4 are output over the signal lines 6 to the digital-to-analog converter 7, which converts the digital input to the step waveform shown in Fig. 3d, which is output on line 8. The waveform of Fig. 3d is amplified by the amplifier 9 or inverted and amplified by the invertor amplifier 10 and presented at the polarity selector switch 11.

The device under test 12 is the semiconductor device, whose breakdown voltage characteristic is to be measured by the apparatus. The electrode from the device under test 12 is connected to the selector switch 11, and another electrode of the device under test 12 is connected to the current detector 13. The output of the current detector 13 which is shown in Fig. 3f, is compared with a reference potential by the comparator 14. When the current passed by the device under test 12 exceeds a preset threshold value, the comparator 14 outputs a step waveform to the single-shot 15 which, in turn, sets the latch 16. The output 17 of latch 16 is connected to an end-of-test indicator and through the invertor 5 to the AND gate 3, such that the presence of an output on line 17 disables the AND gate 3 and stops the counter 4 from incrementing.

During th...