Browse Prior Art Database

Optimizing Use of Shift Register Latch Pair

IP.com Disclosure Number: IPCOM000082680D
Original Publication Date: 1975-Jan-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Mitchell, GR: AUTHOR

Abstract

When utilizing latches of the type shown in U. S. Patent 3,806,891, either output from a latch pair can be used; however; the output of one latch must not feed the same combinatorial logic fed by the output of the other latch forming the latch pair. In view of the restriction, it would normally require two sets of latch pairs for logical operations such as data comparing.

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Optimizing Use of Shift Register Latch Pair

When utilizing latches of the type shown in U. S. Patent 3,806,891, either output from a latch pair can be used; however; the output of one latch must not feed the same combinatorial logic fed by the output of the other latch forming the latch pair. In view of the restriction, it would normally require two sets of latch pairs for logical operations such as data comparing.

A circuit arrangement is shown where both latches of each latch pair are used to store data for a compare function, and still meet the requirement of not feeding the same combinatorial logic. Register 10 consists of latch pairs 15, 30, 40, 50 and 60, where latch pair 60 is representative of the n/th/ position of the register. Data is first entered into register 10 by loading latches 16, 31, 41, 51 and 61 via AND circuits 17, 32, 42, 52 and 62 and OR circuits 18, 33 43, 53 and 63, respectively. The data entered into these latches is then shifted into associated latches 20, 35, 45, 55 and 65.

Latches 16, 31, 41, 51 and 61 are then again loaded, but this time with the comparison data under control of AND circuits 19, 34, 44, 54 and 64 and OR circuits 18, 33, 43, 53 and 63, respectively. The shifting of data from latches 16, 31, 41, 51 and 61 to associated latches 20, 35, 45, 55 and 65 is inhibited. It should also be noted that data bit 0 first loaded into latch 16 and shifted into latch 20, is loaded into latch 31 during the second load of the register. I...