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Generation of Internal Test Signals

IP.com Disclosure Number: IPCOM000082681D
Original Publication Date: 1975-Jan-01
Included in the Prior Art Database: 2005-Feb-28
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Bodner, RE: AUTHOR [+3]

Abstract

Internal test signals for testing a logic module are generated from mutually exclusive signals, without the use of additional module or card pins for test inputs. This arrangement permits full utilization of module pins for logic functions and still enables 100% testability of the module after it has been incorporated into a higher assembly, such as a card or board. The test signals are generated by logically combining signals simultaneously available in the module, but which are mutually exclusive during normal operation. The test signals so generated are then used to test other logic in the module.

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Generation of Internal Test Signals

Internal test signals for testing a logic module are generated from mutually exclusive signals, without the use of additional module or card pins for test inputs. This arrangement permits full utilization of module pins for logic functions and still enables 100% testability of the module after it has been incorporated into a higher assembly, such as a card or board. The test signals are generated by logically combining signals simultaneously available in the module, but which are mutually exclusive during normal operation. The test signals so generated are then used to test other logic in the module.

In Fig. 1, signals A, B, and C are available at pins 10, 11 and 12, respectively. Signals A, B and C during normal operation of the functional logic in the module do not occur simultaneously. Hence, during normal operation of the module, AND circuits 16-22 inclusive, are not conditioned to pass test input signals to the other functional logic, not shown, in the module.

For test purposes, it is possible to make signals A, B and C simultaneously available to satisfy the conditions of AND circuit 16, to provide a Test Input 1 signal. Inverters 13, 14 and 15 enable signals A, B and C to be activated in different combinations to satisfy the inputs of AND circuits 17, 18 and 22. AND circuits 19, 20, and 21 have only two inputs and provide an output signal whenever the input conditions are met.

It is also desirable to be able to test cards without using additional card tab pins for the test signals. Card 30, Fig. 2, is shown with modules 60 and 80 mounted thereon. Signal A is available at tab pin 31 and at module pin 61. Signal B formed...